Deep trench isolation shrinkage method for enhanced device performance

US10325956B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Cheng-Hsien Chou · Tainan, TW
• Shih Pei Chou · Tainan, TW
• Chih-Yu Lai · Tainan, TW
• Sheng-Chau Chen · Tainan, TW
• Chih-Ta Chen · New Taipei, TW
• Yeur-Luen Tu · Taichung, TW
• Chia-Shiung Tsai · Jinshanmian, TW

Key dates

• Filing date: May 10, 2017
• Grant date: Jun 18, 2019
• Expiry date: May 10, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10H20/819

Abstract

Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.