Drain ledge for self-aligned gate and independent channel region and drain-side ridges for SLCFET
US10325982B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
A transistor device comprises a base structure and a superlattice of conducting channels overlying the base structure. The superlattice of conducting channels includes source and drain access regions spaced-apart from each other, a ledge between and spaced-apart from the source and drain access regions, and source-side alternating multichannel ridges and trenches that extend from the source access region to the ledge, each ridge having a topside and opposing sidewalls that each extend from the ledge to the source access region. The transistor device includes gate metal that covers each ridge continuously from the ledge to the source access region, such that the gate metal completely covers the topside of the ridge and edges of the conducting channels that intersect the sidewalls of the ridge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.