TFT device and manufacturing method
US10326027B2 · kind B2 · utility
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5References
7Claims
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Assignee
Inventor
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Aug 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6755
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A TFT device is manufactured starting from a substrate with mutually insulated elongated strips of semi-conductor material. A stack of layers over the strips on the substrate, the stack comprising a gate electrode layer. A multi-level resist layer is provided over the gate electrode layer. The multi-level resist layer defines gate and source drain regions, the channel running in parallel with the direction of the strips. Gate portions in the resist layer cross source drain regions in the resist layer, overreaching the source drain regions on either side at least by a distance corresponding to a pitch of the strips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.