Method and system for DC-DC voltage converters with diminished PWM jitter
US10326354B2 · kind B2 · utility
0Cited by
16References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Oct 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/157
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An embodiment pertains to a method including determining if an amplitude of an error signal has entered steady state. If the amplitude of the error signal has not entered steady state, then amplify with a high gain the amplitude of the AC component of the error signal. If the amplitude of the error signal has entered steady state, then initiate a timer. Determining if the amplitude of the error signal has remained in steady state while the timer runs. If the amplitude of the error signal has remained in steady state while the timer runs, then amplify with a low gain the amplitude of the AC component of the error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.