Level shifter circuit to minimize duty-cycle distortion on clock paths
US10326431B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.