Clock filter and clock processing method
US10326433B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Sep 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock filter filtering a glitch of an input clock to generate an output clock is provided. A first delay circuit inverts the input clock to generate an inverted clock and delays the inverted clock to generate a first processing clock. A second delay circuit delays the input clock to generate a second processing clock. A first setting circuit generates a reset clock according to the inverted clock and the first processing clock. A second setting circuit generates a set clock according to the input clock and the second processing clock. When the set clock changes from a first level to a second level, a third setting circuit sets the output clock at the second level. When the reset clock changes from the first level to the second level, the third setting circuit sets the output clock to the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.