Patent · US Active

Low-power data bus receiver

US10326583B2 · kind B2 · utility

2Cited by

2References

15Claims

0Family size

Assignee

MELEXIS TECHNOLOGIES NV · BE

Inventors

Jörgen STURM · Weimar, DE
Thomas Freitag · Hamburg, DE
Martin Bölter · Erfurt, DE
Anton Babushkin · Kyiv, UA

Key dates

Filing date	May 16, 2018
Grant date	Jun 18, 2019
Priority date	—
Expiry date	May 16, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2012/40215
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.