Ultra-lightweight cryptography accelerator system
US10326587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jul 20, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A cryptography accelerator system includes a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and an on-the-fly hashing circuit to hash data read from a first memory circuit on-the-fly before writing the read data to a second memory circuit. The hashing circuit performs at least one of integrity protection and firmware/software (FW/SW) verification of the data prior to writing the data to the second memory circuit. The on-the-fly hashing circuit includes a bit repositioning circuit to designate an order of bits of a binary word in a register from a most significant bit (MSB) to a least significant bit (LSB) for performing computations without rotating bits in the register, and an on-the-fly round constant generator circuit to generate a round constant from a counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.