Image processor
US10327009B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/44
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.