Method, apparatus, and chip for implementing mutually-exclusive operation of multiple threads
US10331499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Sep 4, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.