Data protection for memory with built-in self-test
US10331530B2 · kind B2 · utility
1Cited by
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21Claims
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Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Jan 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.