Systems and methods for performing memory compression
US10331558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.