Graphics processing unit (GPU) as a programmable packet transfer mechanism
US10331590B2 · kind B2 · utility
40Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.