System and method for arbitration and recovery of SPD interfaces in an information handling system
US10331593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Dec 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system includes a DIMM including a SPD and a slave I2C interface, a processor complex including a first master I2C interface selectively coupled to the slave I2C interface during a system boot state, a BMC including a second master I2C interface selectively coupled to the slave I2C interface during a power-off state, and reset logic configured to select the first master I2C interface to be coupled to the slave I2C interface during the system boot state, select the second master I2C interface to be coupled to the slave I2C interface during the power-off state, detect a transition between the power-off state and the system boot state, and delay the selection of the first master I2C interface to be coupled to the slave I2C interface until the BMC is finished communicating with the SPD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.