ASIC design methodology for converting RTL HDL to a light netlist
US10331835B2 · kind B2 · utility
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4References
5Claims
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Key dates
| Filing date | Jul 7, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Jul 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This application discloses the implementation of a self-timed IP with optional clock-less compression and decompression at the boundaries. It also discloses system and methods for application specific integrated circuits to convert RTL code and timing constraints to self-timed circuitry with optional clock-less compression and decompression at the boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.