Parallel decision tree processor architecture
US10332008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2014 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Apr 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decision tree multi-processor system includes a plurality of decision tree processors that access a common feature vector and execute one or more decision trees with respect to the common feature vector. A related method includes providing a common feature vector to a plurality of decision tree processors implemented within an on-chip decision tree scoring system, and executing, by the plurality of decision tree processors, a plurality off decision trees, by reference to the common feature vector. A related decision tree-walking system includes feature storage that stores a common feature vector and a plurality of decision tree processors that access the common feature vector from the feature storage and execute a plurality of decision trees by comparing threshold values of the decision trees to feature values within the common feature vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.