Computing system and method of performing tile-based rendering of graphics pipeline
US10332231B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Jan 17, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Mar 5, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.