Reset circuit, shift register unit, and gate scanning circuit
US10332434B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 7, 2016 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Nov 7, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset circuit for compensating a level reduction at a first node during a first stage without affecting levels during a second stage includes a reset portion, a reset control portion, and at least three input terminals. The reset portion is coupled to the first and second input terminals, and a second node, and is configured to be turned on if the second node is at a first level, to electrically couple the second and first input terminals. The reset control portion is coupled to the first, second, and third input terminals, and the second node, and is configured to electrically couple the second input terminal with the second node if the first input terminal is at the first level, and to electrically couple the second node with the third input terminal if the second input terminal is at a second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.