Method for manufacturing CMOS structure
US10332804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2015 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Aug 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.