Semiconductor memory device and method of manufacturing the same
US10332890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Jul 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
Abstract
A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.