Semiconductor devices having reduced contact resistance
US10332984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.