Semiconductor device and method of manufacturing semiconductor device
US10332997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Oct 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor device that improves reliability. The impurity concentrations of a p++ source region and a p++ drain region are 5×1020 cm−3 or more. The channel-region-side end portion of a first insulating film is disposed on a p+ source region. The end portion has an inclined surface where the first insulating film thickness is reduced from the p+ source region toward a channel region. The channel-region-side end portion of a second insulating film is disposed on a p+ drain region. The end portion has an inclined surface where the second insulating film thickness is reduced from the p+ drain region toward the channel region. A gate electrode is disposed on the channel region, the p+ source region, the p+ drain region, and the inclined surfaces of the first and the second insulating films through a gate insulating film including an aluminum oxide film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.