Compact high speed duty cycle corrector
US10333527B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Oct 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.