Analog-to-digital converter with noise-shaped dither
US10333543B1 · kind B1 · utility
3Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques that allow application of noise-shaped dither without applying dither at sampling, resulting in the analog-to-digital converter (ADC) circuit advantageously being balanced during acquisition. Balancing the ADC circuit at acquisition can reduce the risk of sampling digital interferences that can couple in through the references or substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.