Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
US10333690B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | May 4, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.