Patent · US Active

Multi-layer integrated circuits having isolation cells for layer testing and related methods

US10338133B2 · kind B2 · utility

2Cited by
3References
18Claims
0Family size

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Inventors

Key dates

Filing dateApr 26, 2017
Grant dateJul 2, 2019
Priority date—
Expiry dateOct 27, 2037

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02P80/30
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes first and second layers that each have one or more electronic components. One or more electronic components of each layer can be electrically connected by a first via and a second via. The integrated circuit also includes an isolation cell operatively connected between the first via and the second via. The isolation cell is configured to controllably break electrical connection between the first via and the second via subsequent to testing of the at least one electronic component of the second layer. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.