Integrated circuit with low power scan system
US10338136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Oct 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.