Power control for use of volatile memory as non-volatile memory
US10338659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Oct 4, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.