Architecture and algorithms for data compression
US10338820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2016 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Aug 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/302
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.