Apparatus and method for controlling rounding when performing a floating point operation
US10338889B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 2016 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Oct 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation, and in addition provides reduce and round circuitry that generates from a supplied floating point value a modified floating point value to be input to the argument reduction circuitry. The reduce and round circuitry is arranged to modify a significand of the supplied floating point value, based on a specified value N, in order to produce a truncated significand with a specified rounding applied, the truncated significand being N bits shorter than the significand of the supplied floating point value, and then being used as a significand for the modified floating point value. The specified value N is chosen such that the argument reduction operation performed using the modified floating point value will inhibit roundoff error in a result of the argument reduction operation. By enabling roundoff error to be inhibited in such a way, it is possible to use such argument reduction circuitry in the computation of a number of floating point operations while enabling the correct rounded result to b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.