Dual-rail delay insensitive asynchronous logic processor with single-rail scan shift enable
US10338930B2 · kind B2 · utility
2Cited by
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16Claims
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Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.