Patent · US Active

Systems and methods for reducing write latency

US10339073B2 · kind B2 · utility

1Cited by
5References
27Claims
0Family size

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Key dates

Filing dateJun 29, 2017
Grant dateJul 2, 2019
Priority date
Expiry dateDec 22, 2037

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F11/0793
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A computer system having reduced write latency and methods for use in computer systems for reducing write latency are provided. Processing circuitry of the computer system is configured to execute a volume filter driver (VFD) that can be switched between a fast termination (FT) mode of operations and a normal, or quiescent, mode of operations. When the processing circuitry receives input/output (IO) write requests to write data to memory while the VFD is in the FT mode of operations, the VFD causes metadata associated with received IO write requests to be written to a volume of memory while preventing actual data associated with received IO write requests from being written to the volume, thereby resulting in extremely fast FT mode operation. After the file has been written to the volume, the VFD enters the quiescent mode of operations during which the VFD passes all IO write requests to the volume.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.