Automated custom circuit layout enhancement
US10339252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Nov 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.