Input-pattern aware reference generation system and computing-in-memory system including the same
US10340003B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jul 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input-pattern aware reference generation system for a memory cell array having a plurality of word lines crossing a plurality of bit lines includes an input counting circuit, a reference array, and a reference word line control circuit. The input counting circuit receives the input signal of the memory cell array, discovers input activated word lines according to the input signal and generates a number signal representing a number of the input activated word lines. The reference array includes a plurality of reference memory cells storing a predetermined set of weights. The reference word line control circuit is electrically connected between the input counting circuit and the reference array. Moreover, the reference word line control circuit controls the reference array to generate a plurality of reference signals being able to distinguish candidates of the computational result of the bit lines in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.