Patterning method for semiconductor device and structures resulting therefrom
US10340141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment method includes defining a first mandrel and a second mandrel over a hard mask layer. The method also includes depositing a spacer layer over and along sidewalls of the first mandrel and the second mandrel, and forming a sacrificial material over the spacer layer between the first mandrel and the second mandrel. The sacrificial material includes an inorganic oxide. The method further includes removing first horizontal portions of the spacer layer to expose the first mandrel and the second mandrel. Remaining portions of the spacer layer provide spacers on sidewalls of the first mandrel and the second mandrel. The method further includes removing the first mandrel and the second mandrel and patterning the hard mask layer using the spacers and the sacrificial material as an etch mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.