Tunable and integrated impedance matching and filter circuit
US10340876B2 · kind B2 · utility
1Cited by
6References
38Claims
0Family size
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Key dates
| Filing date | Feb 19, 2016 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | May 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2007/386
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.