Level shifter
US10340918B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | May 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift includes a bias voltage providing circuit, a level shifting circuit and an output switching circuit. The level shifting circuit includes a high level shifting unit and a low level shifting unit. When the high level shifting unit is in a cut-off state, the high level shifting unit further receives a first bias voltage such that the high level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the high level shifting unit. When the low level shifting unit is in a cut-off state, the low level shifting unit further receives a second bias voltage such that the low level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the low level shifting unit. The level shifter of the present application provides a higher response speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.