Digital locking loop circuit and method of operation
US10340925B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Oct 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.