Phase-locked loop
US10340928B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | May 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for providing improved linearity and reduced noise in a digital phase-locked loop in which a differential time-to-digital converter is implemented. Digital-to-time converters are used for adjusting a reference clock signal based on a fractional change signal and for adjusting a feedback signal based on another fractional change signal. Each fractional change signal is centered about a midpoint, M, and offset from the midpoint by a fraction, x, such that the fractional change signals can be described as (M+x) and (M−x), respectively. By implementing a differential time-to-digital converter, the sum of delays in each input path is kept constant so that integral non-linearity is improved. Supply sensitivity is also reduced, as the same supply is applied to both differential input paths. Since the differential delay can be both positive and negative, the delay range of a differential digital-to-time converter is half that of a single input digital-to-time converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.