Variable step switched capacitor based digital to analog converter incorporating higher order interpolation
US10340940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | May 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.