Flexible ethernet logical lane aggregation
US10341020B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/25
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system or method for logical lane aggregation provides data across a first set of interconnect lanes and determines that at least one interconnect lane is unavailable. The system or method redistributes data to a second set of interconnect lanes, the second set not including the at least one interconnect lane, in response to the at least one interconnect lane being unavailable. The system or method can be used to provide flexible Ethernet logical lane aggregation (FELLA).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.