Fast settling bias circuit
US10345845B1 · kind B1 · utility
1Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Apr 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure include systems, methods, devices, and circuits for fast settling of a bias node. Consistent with some embodiments, a bias circuit may include a successive-approximation-register-analog-to-digital converter (SAR-ADC) based settling loop configured to perform a fast settling process for a heavily loaded bias node. The SAR-ADC based loop performs a SAR-ADC process that includes measuring a reference signal to determine a number of cells in a capacitor array that are involved in a charge sharing process while simultaneously completing the settling process for the bias node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.