Forcing a processor into a low power state
US10345889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Aug 4, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.