Providing multiple memory modes for a processor including internal memory
US10346300B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Jun 21, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Sep 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.