DDR4 memory I/O driver
US10347325B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Jun 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a DDR4 memory I/O driver including a pre-driver, a pull-up circuit and a pull-down circuit. The pre-driver is coupled between a first high voltage terminal and a low voltage terminal to provide a first and a second pre-driving signals. The pull-up circuit includes: a driving PMOS transistor coupled between a second high voltage terminal and a pull-up resistor, that is coupled to an output pad, to operate according to the first pre-driving signal, in which the second high voltage terminal's voltage is not higher than the first high voltage terminal's voltage. The pull-down circuit includes: a driving NMOS transistor coupled between the low voltage terminal and a cascode NMOS transistor to operate according to the second pre-driving signal; and the cascode NMOS transistor coupled between the driving NMOS transistor and a pull-down resistor, that is coupled to the output pad, to operate according to a bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.