Method of forming interconnect structure with partial copper plating
US10347530B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 17, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Nov 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a dielectric layer on the substrate, the dielectric layer having an opening extending to the substrate. The method further includes forming a mask layer on at least one portion of the dielectric layer, forming a metal layer filling the opening and covering portions of dielectric layer not covered by the mask layer, removing the mask layer, and planarizing the metal layer so that an upper surface of a remaining portion of the metal layer is flush with an upper surface of the dielectric layer. The method can mitigate the warping problems of the substrate associated with the fabrication of the interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.