Fan-out semiconductor package
US10347613B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | May 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes first and second structures. The first structure includes a first semiconductor chip, a first encapsulant, and a connection member. The second structure includes a second semiconductor chip, a second encapsulant, and conductive bumps. The first and second structures are disposed so that active surfaces of the first and second semiconductor chips face each other. The conductive bumps are electrically connected to a redistribution layer, and connection pads of the first and second semiconductor chips are connected to each other through the redistribution layer in a signal manner. Signal transmission times between one point of the redistribution layer and connection pads of each of the first and second semiconductor chips are substantially the same as each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.