Field effect transistor contact with reduced contact resistance using implantation process
US10347762B1 · kind B1 · utility
10Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.