Split gate non-volatile memory (NVM) with improved programming efficiency
US10347773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2017 |
| Grant date | Jul 9, 2019 |
| Priority date | — |
| Expiry date | Nov 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Device and method of forming a non-volatile memory (NVM) device are disclosed. The NVM device includes NVM cells disposed on a substrate in a device region. The NVM cell includes a floating gate (FG) with first and second FG sidewalls disposed on the substrate and an intergate dielectric layer disposed over the FG and substrate. Re-entrants are disposed at corners of the intergate dielectric which are filled by dielectric re-entrant spacers. An access gate (AG) with first and second AG sidewalls is disposed on the substrate adjacent to the FG such that the second AG sidewall is adjacent to a first FG sidewall and separated by the intergate dielectric layer and the re-entrant spacers prevent AG from filling the re-entrants. A first source/drain (S/D) region is disposed in the substrate adjacent to the first AG sidewall and a second S/D region is disposed in the substrate adjacent to the second FG sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.