Wafer-scale integration of vacancy centers for spin qubits

US10347834B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Nicole K. Thomas · Portland, US
• Marko Radosavljevic · Portland, US
• Sansaptak Dasgupta · Hillsboro, US
• Ravi Pillarisetty · Portland, US
• Kanwaljit Singh · Rotterdam, NL
• Hubert C. George · Portland, US
• Jeanette M. Roberts · North Plains, US
• David J. Michalak · Portland, US
• Roman Caudillo · Portland, US
• Zachary R. Yoscovits · Beaverton, US
• Lester Lampert · Portland, US
• James S. Clarke · Portland, US

Key dates

• Filing date: Mar 22, 2018
• Grant date: Jul 9, 2019
• Expiry date: Mar 22, 2038

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/933
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Embodiments of the present disclosure propose two methods for integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. The first method is based on using a self-assembly process for integrating VC islands on a semiconductor substrate. The second method is based on using a buffer layer of a III-N semiconductor material over a semiconductor substrate, and then integrating VC islands in an insulating carbon-based material such as diamond that is either grown as a layer on the III-N buffer layer or grown in the openings formed in the III-N buffer layer. Integration of VC islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.